The present invention relates to a three stage nonblocking switching array for a plurality of input lines, which is of the type including an input stage having a plurality of sub-arrays with inputs and outputs, an intermediate stage having a plurality of sub-arrays with inputs and outputs, and an output stage having a plurality of sub-arrays with inputs and outputs, with the input lines being distributed to the inputs of the input stage. Such switching arrays are known from an article by Charles Clos, "A Study of Non-Blocking Switching Networks", Bell System Technical Journal, Vol. XXXII, 1953, pages 406-425, and U.S. Pat. No. 3,978,291, incorporated herein by reference.
Switching arrays of the type disclosed in the above publications are constructed in three stages, with each stage being comprised of a plurality of sub-arrays. Assuming the switching array as a whole has N input lines and N output lines to be selectively interconnected, by meeting certain conditions, it is possible in a three-stage structured array to keep the number of crosspoints or interconnections lower than N.sup.2 while still providing an array exhibiting non-blocking characteristics.
It is possible, in principle, to construct a switching array having non-blocking characteristics by modification of a switching array which is otherwise not blockage free through expansion, for example by doubling the number of crosspoints. However, this involves a considerable amount of additional expenditure.